TRAPEDS address tracing and its application to multicomputer cache performance analysis

Trace-driven simulation is an important aid in performance analysis of computer systems. Capturing address traces to use in these simulations, however, is a difficult problem, particularly for parallel processor architectures. Even when trace capture methods are applicable to parallel processors, the amount of collected data typically grows with the number of processors, thus increasing I/O and tracer storage costs. This thesis presents a new technique called TRAPEDS which modifies executable code (at the assembly language level) to dynamically collect the address trace from both the user code and the operating system and analyzes this trace during the execution of the program. This method helps resolve the I/O and storage limitations and facilitates concurrent analysis of the address trace. Implementation of TRAPEDS on the Intel iPSC/2 hypercube multicomputer is described. A method for minimizing the effect of tracing on the processor interaction ion the iPSC/2 is also introduced.This thesis presents cache simulation results generated from address traces collected for applications running on the iPSC/2. The emphasis of the cache performance study is understanding the effect of changing the number of processing nodes that are cooperating to execute a given application. The effects on multicomputer cache performance of several application characteristics, such as data partitioning, data access patterns, communication patterns, and communication frequency, are illustrated.U of I OnlyETDs are only available to UIUC Users without author permissio