Synthetic Address Trace Generation for Multiprocessor Systems

We propose a synthetic address trace generation model which combine the accuracy advantage of trace-driven simulation and the low complexity advantage of discrete event simulation. The model provides flexibility in characterizing the system workload independent of cache structure. The generatedaddress references not only synthesize the temporal and spatial locality behaviorbut also consider the data sharing characteristics of multiprocessor systems. 1 Introduction Trace-driven simulation is a popular tool for computer system evaluation. It provides an accurate performance assessmentin cache coherency protocols and other system design issues. However, this technique requires a parallel trace for multiprocessor systems which is difficult and expensive to obtain. Although different techniques in gathering program traces and in reducing the complexity of tracedriven simulation have been developed [1, 2, 3, 4], the complexity of this technique increases as the system size increases due to ..