Efficient Address Translation Simulation

. In this paper we describe the implementation of a multithreaded trace-driven address translation simulator built using Object Oriented (OO) and design pattern principles. Address translation mechanisms generally use a cache-based translation lookaside buffer of recent translations of process virtual addresses to physical addresses. More diverse regimes are possible but are not generally handled by available simulators. Our approach yields four major improvements over existing cache simulators encompassing: parallel analysis of alternate regimes, diverse translation structures, operating system support polices, and rapid prototyping. A series of tests conducted on our multi-processor servers have shown speed increases proportional to the number of processors available. Keywords Computer Architecture, Memory Management, Address Translation, Object Oriented Design, Simulation 1 Introduction The term virtual memory describes the ability to address greater amounts of memory than that whi..