VLSI implementation of neural networks based on PN sequences

We present a method of computing inner-products using PN sequences which we apply to neural network implementations. The accuracy of the results and speed can be traded off by varying the length of the sequences. A neural network architecture based on this scheme has several advantages. The weight matrix and the neuron state vector are stored as binary numbers and then coded into sequences of 1\u27s and 0\u27s. This results in low hardware complexity enabling several neurons to be implemented on a single chip. Also, intermediate results of the computations are available continously and provide us with estimates to update the state of the neurons. Sampling the output of the computations at short intervals, and then gradually increasing the sampling interval helps to dislodge the neural network from local minima and possibly finally enter into a global stable state