Execution of neural network algorithms on an array of bit-serial processors

Large processor arrays are candidates for performing computations of neural network models at speeds required for real time applications, e.g. in pattern recognition. The paper gives a general model of an array of bit-serial processors and demonstrates the mapping of neural net models on such an array. The approach maps a neuron on each processing element and makes communication all-to-all available by connection weight matrices. The required communication structure is very simple. The bit-serial approach allows trade-offs between speed and precision, even dynamically. Performance figures are given. A bitserial multiplier is an important part of the design. Implementation aspects are discussed and it is shown that a one-board realization of a 1024 processor system is feasible with current, commonly available, technology.Godkänd; 1990; 20080425 (ysko)