Optimization outside of traditional frameworks is emerging as a new research focus in the compiler construction community. Scheduled assembly code is one area of increased interest. Optimization cannot be performed without a control-flow graph (CFG), and current CFG construction algorithms can fail on scheduled code. We present a new construction algorithm that correctly constructs CFGs and permits meaningful optimization for scheduled code. One potential post-compilation optimization is reducing power consumption by minimizing switching activity on the instruction bus. We designed and implemented an algorithm that attempts to minimize switching activity by renaming registers for Texas Instruments' TMS320C6200 processor. We gathered results...
[[abstract]]©2007 ACM-Power leakage constitutes an increasing fraction of the total power consumptio...
This paper is to develop an innovative technique using dynamic voltage scaling (DVS) to reduce the e...
We investigate the problem of code generation for DSP systems on a chip. Such systems devote a limit...
A variety of applications have arisen where it is worthwhile to apply code optimizations directly to...
Power leakage constitutes an increasing fraction of the total power consumption in modern semiconduc...
[[abstract]]Power leakage constitutes an increasing fraction of the total power consumption in moder...
[[abstract]]Power leakage constitutes an increasing fraction of the total power consumption in moder...
Dynamic voltage and frequency scaling has been identified as one of the most effective ways to reduc...
Modern compilers typically optimize for executable size and speed, rarely exploring non-functional p...
The increasing need for low-power computing devices has led to the efforts to optimize power in all ...
Abstract--- Energy efficiency is becoming increasingly important for computation, especially in the ...
[[abstract]]We investigate compiler transformation techniques for the problem of scheduling VLIW ins...
Abstract—Optimizing for energy constraints is of critical importance due to the proliferation of bat...
Superscalar processors contain large, complex structures to hold data and instructions as they wait ...
We propose a classification of high and low-level compiler optimizations to reduce the clock period,...
[[abstract]]©2007 ACM-Power leakage constitutes an increasing fraction of the total power consumptio...
This paper is to develop an innovative technique using dynamic voltage scaling (DVS) to reduce the e...
We investigate the problem of code generation for DSP systems on a chip. Such systems devote a limit...
A variety of applications have arisen where it is worthwhile to apply code optimizations directly to...
Power leakage constitutes an increasing fraction of the total power consumption in modern semiconduc...
[[abstract]]Power leakage constitutes an increasing fraction of the total power consumption in moder...
[[abstract]]Power leakage constitutes an increasing fraction of the total power consumption in moder...
Dynamic voltage and frequency scaling has been identified as one of the most effective ways to reduc...
Modern compilers typically optimize for executable size and speed, rarely exploring non-functional p...
The increasing need for low-power computing devices has led to the efforts to optimize power in all ...
Abstract--- Energy efficiency is becoming increasingly important for computation, especially in the ...
[[abstract]]We investigate compiler transformation techniques for the problem of scheduling VLIW ins...
Abstract—Optimizing for energy constraints is of critical importance due to the proliferation of bat...
Superscalar processors contain large, complex structures to hold data and instructions as they wait ...
We propose a classification of high and low-level compiler optimizations to reduce the clock period,...
[[abstract]]©2007 ACM-Power leakage constitutes an increasing fraction of the total power consumptio...
This paper is to develop an innovative technique using dynamic voltage scaling (DVS) to reduce the e...
We investigate the problem of code generation for DSP systems on a chip. Such systems devote a limit...