Power-Aware Compilation with Architectural Support and Instruction Scheduling Yu-Ting Hung

This paper is to develop an innovative technique using dynamic voltage scaling (DVS) to reduce the energy dissipation. The objective of our work is to maximize the period of idle functional units and minimize the transitions between power modes. To achieve this goal, our work is performed in the following steps. First, the program will be built as a control flow graph that comprises many regions. Second, we build the power model of the program and collect the power information by profiling the control flow graph. Then the regions with the same functional units will be merged if the merging still preserves the program dependencies. Next, the idle functional units will be turned off and each region will be assigned a power mode based on the power model. Finally, the program is rescheduled to merge the regions to reduce the transitions between power modes. Our work is implemented on the basis of SUIF2 compiler infrastructure and the Wattach simulator and measured by using SPEC2000, DSPstone, and JPEG decoder as benchmarks. On average, the experimental results show that our work can save the energy by 26 % with performance degradation between 5 % and 18%