Hardware Acceleration of Real-Life Applications: from Theory to Implementation

There has been a lot of research to support the benefits of reconfigurable hardware acceleration in high performance low power System-on-Chips. Despite numerous advances made over the last two decades, especially in code generation support, reconfigurable system-on-chips still face application programming challenges. As the full automated synthesis of real-world applications such as digital video coding is still not supported for complexity reasons, acceleration is likely to occur as an execution of software code and dedicated hardware involving large amounts of data communication. These overheads alter significantly the benefits of hardware acceleration and usually requires important hardware expertise. In these conditions, a bottleneck lies in the fast implementation of optimised on-chip bus interfaces, indeed this time consuming hardware (and software) development process reflects critically on performance, but also on development and debug efforts. This paper proposes a design flow for reconfigurable hardware acceleration in which a specific topology for C/C++ function arguments is set to help the generation of on-chip bus compliant interface, on top of High Level Synthesis (HLS). We show how struc-turing data arguments allows the definition of a generic bus wrapper interface for accelerators produced by HLS. We additionally illustrate the effectiveness of this approach on the practical implementation example of a full H264/AVC profile video decoder in recent FPGA-embedded systems considering PLB and AXI bus protocols