Checking the equivalence of two Boolean functions, or combinational circuits modeled as Boolean functions, is often desired when reliable and correct hardware components are required. The most common approaches to equivalence checking are based on simulation and model checking, which are constrained due to the popular memory and state explosion problems. Furthermore, such tools are often not user-friendly, thereby making it tedious to check the equivalence of large formulas or circuits. An alternative is to use mathematical tools, called interactive theorem provers, to prove the equivalence of two circuits; however, this requires human effort and expertise to write multiple output functions and carry out interactive proof of their equivalen...
Abstract. We propose a new library to model and verify hardware cir-cuits in the Coq proof assistant...
ABSTRACT: Formal methods for the verification of Integrated Circuits (ICs) are a collection of techn...
Abstract. We propose a new library to model and verify hardware cir-cuits in the Coq proof assistant...
Abstract — The combinational logic-level equivalence problem is to determine whether two given combi...
The paper explores several ways to improve the speed and capacity of combinational equivalence check...
Abstract. In this report we develop a theory of equivalence checking and logic synthesis of circuits...
ABSTRACT. In this paper we develop a theory of equivalence checking (EC) and logic synthesis of circ...
In this paper we discuss the development of a BDD-based verification engine for combinational equiva...
We propose a novel technique to improve SAT-based Combinational Equivalence Checking (CEC). The idea...
The ever shrinking feature size of modern electronic chips leads tomore designs being done as well a...
This dissertation investigates the problems of two distinctive formal verification techniques for ve...
Functional verification is an important phase in the design flow of digital circuits as it is used t...
ABSTRACT Threshold logic is gaining prominence as an alternative to Boolean logic. The main reason f...
Today's digital systems are at the forefront of modern technology. Electronic chips with a billion t...
We propose a new library to model and verify hardware circuits in the Coq proof assistant. This libr...
Abstract. We propose a new library to model and verify hardware cir-cuits in the Coq proof assistant...
ABSTRACT: Formal methods for the verification of Integrated Circuits (ICs) are a collection of techn...
Abstract. We propose a new library to model and verify hardware cir-cuits in the Coq proof assistant...
Abstract — The combinational logic-level equivalence problem is to determine whether two given combi...
The paper explores several ways to improve the speed and capacity of combinational equivalence check...
Abstract. In this report we develop a theory of equivalence checking and logic synthesis of circuits...
ABSTRACT. In this paper we develop a theory of equivalence checking (EC) and logic synthesis of circ...
In this paper we discuss the development of a BDD-based verification engine for combinational equiva...
We propose a novel technique to improve SAT-based Combinational Equivalence Checking (CEC). The idea...
The ever shrinking feature size of modern electronic chips leads tomore designs being done as well a...
This dissertation investigates the problems of two distinctive formal verification techniques for ve...
Functional verification is an important phase in the design flow of digital circuits as it is used t...
ABSTRACT Threshold logic is gaining prominence as an alternative to Boolean logic. The main reason f...
Today's digital systems are at the forefront of modern technology. Electronic chips with a billion t...
We propose a new library to model and verify hardware circuits in the Coq proof assistant. This libr...
Abstract. We propose a new library to model and verify hardware cir-cuits in the Coq proof assistant...
ABSTRACT: Formal methods for the verification of Integrated Circuits (ICs) are a collection of techn...
Abstract. We propose a new library to model and verify hardware cir-cuits in the Coq proof assistant...