ABSTRACT. In this paper we develop a theory of equivalence checking (EC) and logic synthesis of circuits with a common specification (CS). We show that two combinational circuits N 1, N 2 have a CS iff they can be partitioned into subcircuits that are connected “in the same way ” and are toggle equivalent. This fact allows one to represent a specification of a circuit implicitly as a partitioning into subcircuits. We give an efficient procedure for checking if circuits N 1, N 2 have the same predefined specification. As a “by-product”, this procedure performs EC of N 1 and N 2. We show how, given a circuit N 1 with a predefined specification, one can efficiently build a circuit N 2 satisfying the same specification. We give experimental evi...
This thesis is concerned with the utilization of formal verification techniques in the design of the...
Summary. In the paper we investigate the dependence between the structure of circuits and sets of te...
In this paper, we address the problem of verifying the equivalence of two sequential circuits. State...
Abstract. In this report we develop a theory of equivalence checking and logic synthesis of circuits...
Checking the equivalence of two Boolean functions, or combinational circuits modeled as Boolean func...
This paper presents a method for verifying that two hierarchical combinational circuits implement th...
Abstract — The combinational logic-level equivalence problem is to determine whether two given combi...
Abstract — Combinational equivalence checking is an essential task in circuit design. In this paper ...
Iterative retiming and resynthesis is a powerful way to optimize se-quential circuits but its massiv...
In this paper we solve the problem of identify-ing a \matching " between two logic circuits or ...
Checking the functional equivalence of sequential circuits is an important practical problem. Becaus...
We introduce a new equivalence checking method based on abstract BDDs (aBDDs). The basic idea is the...
Verifying the equivalence of sequential circuits is computationally expensive. Therefore it is inter...
One application of equivalence checking is to establish correspondence between a high-level, abstrac...
This paper presents an efficient formal logic verification algorithm for combinational circuits. Our...
This thesis is concerned with the utilization of formal verification techniques in the design of the...
Summary. In the paper we investigate the dependence between the structure of circuits and sets of te...
In this paper, we address the problem of verifying the equivalence of two sequential circuits. State...
Abstract. In this report we develop a theory of equivalence checking and logic synthesis of circuits...
Checking the equivalence of two Boolean functions, or combinational circuits modeled as Boolean func...
This paper presents a method for verifying that two hierarchical combinational circuits implement th...
Abstract — The combinational logic-level equivalence problem is to determine whether two given combi...
Abstract — Combinational equivalence checking is an essential task in circuit design. In this paper ...
Iterative retiming and resynthesis is a powerful way to optimize se-quential circuits but its massiv...
In this paper we solve the problem of identify-ing a \matching " between two logic circuits or ...
Checking the functional equivalence of sequential circuits is an important practical problem. Becaus...
We introduce a new equivalence checking method based on abstract BDDs (aBDDs). The basic idea is the...
Verifying the equivalence of sequential circuits is computationally expensive. Therefore it is inter...
One application of equivalence checking is to establish correspondence between a high-level, abstrac...
This paper presents an efficient formal logic verification algorithm for combinational circuits. Our...
This thesis is concerned with the utilization of formal verification techniques in the design of the...
Summary. In the paper we investigate the dependence between the structure of circuits and sets of te...
In this paper, we address the problem of verifying the equivalence of two sequential circuits. State...