Reasoning about High-Level Constructs in Hardware/Software Formal Verification

The ever shrinking feature size of modern electronic chips leads tomore designs being done as well as more complex chips beingdesigned. These in turn lead to greater use of high-levelspecifications and to more sophisticated optimizations applied at theword -level. These steps make it more difficult to verify that thefinal design is faithful to the initial specification. We tackle twosteps in this process and their formal equivalence checking to helpverify the correctness of the steps.First, we present LEC, a combinational equivalence checking tool that is learning driven. It focuses on data-path equivalencechecking with the goal of transforming the two logics under comparison to be moresimilar in order to reduce the complexity of a final Boolean (bit-level)solving. LEC does equivalence checking of combinational logic between two RTL (word-level) designs, one the original and one an optimized RTL version. LEC features an open architecture such that users and developers canlearn with the system as new designs and optimizations are met, and then it can be modularly extended with new proof procedures as they are discovered. To address the use of higher level specifications, we build a simple trusted C to Verilog translation procedure based on theLLVM compiler infrastructure. The translator was designed to implement an almost vertatimtranslation of the C language operators and control structures intothe Verilog \emph{always\_ff} and \emph{always\_comb} blocks through traversing LLVMBytecode programs. The procedure reliably bridges the language barrierbetween software and hardware and allows hardware synthesisand verification techniques to be applied readily.In combination, these two procedures allow for equivalence checkingbetween a software-like specification and an optimized word-level RTLimplementation