Fabricating and testing a VLSI systolic convolution cell for image processing

The two-dimensional discrete convolution operator is targeted for performance improvement in order to speed up image processing work loads. Since the large computation requirements for this operation are especially taxing to single processor computers, the approach is to consider parallel processing alternatives. Of the parallel processor classes considered, systolic arrays are singled out as the preferred parallel processing solution for the convolution problem.Therefore, the design of a pipelined double precision floating point VLSI systolic cell for convolution is described. The arithmetic operations are distributed into three pipelined stages, enabling the cell to process each set of operands within 16 clock cycles. Once fabricated and tested, the systolic chip yielded an 80 MFLOPS performance which is a remarkable improvement over available general purpose computers