Tuning synthesis flags to optimize implementation goals: Performance and robustness of the LEON3 processor as a case study

[EN] The steady growth in complexity of FPGAs has led designers to rely more and more on manufacturers¿ and third parties¿ design tools to meet their implementation goals. However, as modern synthesis tools provide a myriad of different optimization flags, whose contribution towards each implementation goal is not clearly accounted for, designers just make use of a handful of those flags. This paper addresses the challenging problem of determining the best configuration of available synthesis flags to optimize the designer¿s implementation goals. First, fractional factorial design is used to reduce the whole design space. Resulting configurations are implemented to estimate the actual impact, and statistical significance, of each considered synthesis flag. After that, multiple regression analysis techniques predict the expected outcome for each possible combination of these flags. Finally, multiple-criteria decision making techniques enable the selection of the best set of synthesis flags according to explicitly defined implementation goals.This work has been partially funded by the Ministerio de Economia, Industria y Competitividad de Espana under grant agreement no. TIN2016-81075-R, and the "Programa de Ayudas de Investigacion y Desarrollo" (PAID) de la Universitat Politecnica de Valencia.Tuzov, I.; Andrés, DD.; Ruiz, JC. (2018). Tuning synthesis flags to optimize implementation goals: Performance and robustness of the LEON3 processor as a case study. Journal of Parallel and Distributed Computing. 112:84-96. https://doi.org/10.1016/j.jpdc.2017.10.002S849611