EDIF netlist optimization of pipelined designs

This thesis describes the design, implementation, and evaluation of a software system for optimizing synthesized logic circuits. The particular implementation described is targeted to the Xilinx Virtex family of FPGAs, but the techniques developed are relevant to other families of array-based semi-custom programmable logic circuits. One of the unique aspects of my approach is that the optimization occurs after the circuit is mapped onto the logic array. Prior to this work it was commonly believed that optimization after mapping was infeasible. The advantages of this approach include the ability to optimize a design without having the VHDL source code, the opportunity to selectively optimize only parts of a circuit and the preservation of the original the state encoding. The optimizations are also transparent to the synthesis process. This is a powerful and versatile method, which gives the designer considerable freedom in optimizing parts of the design according to his or her preferences. The optimization process proceeds as follows. The behavioral or structural description of the design is first written in VHDL. The design is then synthesized using the Workview Office synthesis tool and extracted to an EDIF (Electronic Design Interface Format) mapped netlist targeting Xilinx's Virtex family of FPGAs. This netlist is then analyzed, and an internal representation of the given circuit is created. Any pipelines (blocks of combinational logic feeding one or more registers) that exist in the circuit are then identified and common blocks of logic that reside between the pipeline registers are extracted. Multilevel minimization algorithms in the SIS framework are applied in order to optimize the design. The optimized equations are then converted to an EDIF-compatible format and all the necessary modifications are computed in order to restructure the original netlist to produce the optimized one. The resultant remapped circuit is then placed and routed as before