Toward Speculative Loop Pipelining for High-Level Synthesis

International audienceLoop pipelining is a key optimization in modern HLS tools for synthesizing efficient hardware datap-aths. Existing techniques for automatic loop pipelining are limited by static analysis that cannot precisely analyze loops with data-dependent control-flow and/or memory accesses. We propose a technique for speculative loop pipelining that handles both control-flow and memory speculations in a unified manner. Our approach is entirely expressed at the source-level, allowing a seamless integration to development flows using HLS. Our evaluation shows significant improvement in throughput over standard loop pipelining