Modern architectures provide weaker memory consistency guarantees than sequential consistency. These weaker guarantees allow programs to exhibit behaviours where the program statements appear to have executed out of program order. Fortunately, modern architectures provide memory barriers (fences) to enforce the program order between a pair of statements if needed. Due to the intricate semantics of weak memory models, the placement of fences is challenging even for experienced programmers. Too few fences lead to bugs whereas overuse of fences results in performance degradation. This motivates automated placement of fences. Tools that restore sequential consistency in the program may insert more fences than necessary for the program to be cor...
The work covered in this thesis concerns automatic analysis of correctness of parallel programs runn...
Many modern multicore architectures support shared mem-ory for ease of programming and relaxed memor...
To enhance performance, common processors feature relaxed memory models that reorder instructions. H...
Modern architectures provide weaker memory consistency guarantees than sequential consistency. These...
Modern architectures provide weaker memory consistency guarantees than sequential consistency. These...
Abstract. Modern architectures provide weaker memory consistency guarantees than sequential consiste...
Abstract—This paper addresses the problem of placing mem-ory fences in a concurrent program running ...
For efficiency reasons, most modern processor architectures allow the reordering of CPU instructions...
Abstract—We observe that fence instructions used by pro-grammers are usually only intended to order ...
Fences are instructions that programmers or compilers insert in the code to prevent the compiler or ...
Shared memory has been widely adopted as the primary system level programming abstraction on modern ...
Modern architectures rely on memory fences to prevent undesired weakenings of memory consistency. As...
Abstract. We address the problem of fence inference in infinite-state concur-rent programs running o...
Cache coherence protocols based on self-invalidation and self-downgrade haverecently seen increased ...
International audienceCache coherence protocols using self-invalidation and self-downgrade have rece...
The work covered in this thesis concerns automatic analysis of correctness of parallel programs runn...
Many modern multicore architectures support shared mem-ory for ease of programming and relaxed memor...
To enhance performance, common processors feature relaxed memory models that reorder instructions. H...
Modern architectures provide weaker memory consistency guarantees than sequential consistency. These...
Modern architectures provide weaker memory consistency guarantees than sequential consistency. These...
Abstract. Modern architectures provide weaker memory consistency guarantees than sequential consiste...
Abstract—This paper addresses the problem of placing mem-ory fences in a concurrent program running ...
For efficiency reasons, most modern processor architectures allow the reordering of CPU instructions...
Abstract—We observe that fence instructions used by pro-grammers are usually only intended to order ...
Fences are instructions that programmers or compilers insert in the code to prevent the compiler or ...
Shared memory has been widely adopted as the primary system level programming abstraction on modern ...
Modern architectures rely on memory fences to prevent undesired weakenings of memory consistency. As...
Abstract. We address the problem of fence inference in infinite-state concur-rent programs running o...
Cache coherence protocols based on self-invalidation and self-downgrade haverecently seen increased ...
International audienceCache coherence protocols using self-invalidation and self-downgrade have rece...
The work covered in this thesis concerns automatic analysis of correctness of parallel programs runn...
Many modern multicore architectures support shared mem-ory for ease of programming and relaxed memor...
To enhance performance, common processors feature relaxed memory models that reorder instructions. H...