Abstract—This paper addresses the problem of placing mem-ory fences in a concurrent program running on a relaxed memory model. Modern architectures implement relaxed memory models which may reorder memory operations or execute them non-atomically. Special instructions called memory fences are provided to the programmer, allowing control of this behavior. To ensure correctness of many algorithms, in particular of non-blocking ones, a programmer is often required to explicitly insert memory fences into her program. However, she must use as few fences as possible, or the benefits of the relaxed architecture may be lost. Placing memory fences is challenging and very error prone, as it requires subtle reasoning about the underlying memory model....
Abstract. We present a new abstract interpretation based approach for automat-ically verifying concu...
Memory fences inhibit the reordering of memory accesses in modern microprocessors; fences are useful...
A memory model for a concurrent imperative programming lan-guage specifies which writes to shared va...
Modern architectures implement relaxed memory models which may reorder memory operations or execute ...
For efficiency reasons, most modern processor architectures allow the reordering of CPU instructions...
The work covered in this thesis concerns automatic analysis of correctness of parallel programs runn...
Abstract. We address the problem of fence inference in infinite-state concur-rent programs running o...
Modern architectures provide weaker memory consistency guarantees than sequential consistency. These...
Modern architectures provide weaker memory consistency guarantees than sequential consistency. These...
Abstract. Modern architectures provide weaker memory consistency guarantees than sequential consiste...
Traditional memory fences are program-based. That is, a mem-ory fence enforces a serialization point...
Many modern multicore architectures support shared mem-ory for ease of programming and relaxed memor...
To enhance performance, common processors feature relaxed memory models that reorder instructions. H...
Shared memory has been widely adopted as the primary system level programming abstraction on modern ...
Concurrency libraries can facilitate the development of multithreaded programs by providing concurre...
Abstract. We present a new abstract interpretation based approach for automat-ically verifying concu...
Memory fences inhibit the reordering of memory accesses in modern microprocessors; fences are useful...
A memory model for a concurrent imperative programming lan-guage specifies which writes to shared va...
Modern architectures implement relaxed memory models which may reorder memory operations or execute ...
For efficiency reasons, most modern processor architectures allow the reordering of CPU instructions...
The work covered in this thesis concerns automatic analysis of correctness of parallel programs runn...
Abstract. We address the problem of fence inference in infinite-state concur-rent programs running o...
Modern architectures provide weaker memory consistency guarantees than sequential consistency. These...
Modern architectures provide weaker memory consistency guarantees than sequential consistency. These...
Abstract. Modern architectures provide weaker memory consistency guarantees than sequential consiste...
Traditional memory fences are program-based. That is, a mem-ory fence enforces a serialization point...
Many modern multicore architectures support shared mem-ory for ease of programming and relaxed memor...
To enhance performance, common processors feature relaxed memory models that reorder instructions. H...
Shared memory has been widely adopted as the primary system level programming abstraction on modern ...
Concurrency libraries can facilitate the development of multithreaded programs by providing concurre...
Abstract. We present a new abstract interpretation based approach for automat-ically verifying concu...
Memory fences inhibit the reordering of memory accesses in modern microprocessors; fences are useful...
A memory model for a concurrent imperative programming lan-guage specifies which writes to shared va...