Fences are instructions that programmers or compilers insert in the code to prevent the compiler or the hardware from reordering memory accesses [20, 43]. Fences can be expensive because all of the accesses before the fence have to be finished (i.e., the loads have to be retired and the writes drained from the write buffer) before any access after the fence can be observed by any other processor. This thesis seeks to reduce the fence overhead in relaxed-consistency machines. It first introduces the WeeFence, a fence that is very cheap because it allows post-fence accesses to skip it. Such accesses can typically complete and retire before the pre-fence writes have drained from the write buffer. Only when an incorrect reordering of accesse...
International audienceWe present a class of relaxed memory models, defined in Coq, parameterised by ...
Cache coherence protocols based on self-invalidation and self-downgrade haverecently seen increased ...
Concurrency libraries can facilitate the development of multithreaded programs by providing concurre...
Fences are instructions that programmers or compilers insert in the code to prevent the compiler or ...
Modern architectures rely on memory fences to prevent undesired weakenings of memory consistency. As...
Modern architectures provide weaker memory consistency guarantees than sequential consistency. These...
Modern architectures provide weaker memory consistency guarantees than sequential consistency. These...
Shared memory has been widely adopted as the primary system level programming abstraction on modern ...
Abstract. Modern architectures provide weaker memory consistency guarantees than sequential consiste...
Modern architectures rely on memory fences to prevent undesired weakenings of memory consistency. As...
Memory fences inhibit the reordering of memory accesses in modern microprocessors; fences are useful...
International audienceCache coherence protocols using self-invalidation and self-downgrade have rece...
For efficiency reasons, most modern processor architectures allow the reordering of CPU instructions...
There have been several recent efforts to improve the per-formance of fences. The most aggressive de...
To enhance performance, common processors feature relaxed memory models that reorder instructions. H...
International audienceWe present a class of relaxed memory models, defined in Coq, parameterised by ...
Cache coherence protocols based on self-invalidation and self-downgrade haverecently seen increased ...
Concurrency libraries can facilitate the development of multithreaded programs by providing concurre...
Fences are instructions that programmers or compilers insert in the code to prevent the compiler or ...
Modern architectures rely on memory fences to prevent undesired weakenings of memory consistency. As...
Modern architectures provide weaker memory consistency guarantees than sequential consistency. These...
Modern architectures provide weaker memory consistency guarantees than sequential consistency. These...
Shared memory has been widely adopted as the primary system level programming abstraction on modern ...
Abstract. Modern architectures provide weaker memory consistency guarantees than sequential consiste...
Modern architectures rely on memory fences to prevent undesired weakenings of memory consistency. As...
Memory fences inhibit the reordering of memory accesses in modern microprocessors; fences are useful...
International audienceCache coherence protocols using self-invalidation and self-downgrade have rece...
For efficiency reasons, most modern processor architectures allow the reordering of CPU instructions...
There have been several recent efforts to improve the per-formance of fences. The most aggressive de...
To enhance performance, common processors feature relaxed memory models that reorder instructions. H...
International audienceWe present a class of relaxed memory models, defined in Coq, parameterised by ...
Cache coherence protocols based on self-invalidation and self-downgrade haverecently seen increased ...
Concurrency libraries can facilitate the development of multithreaded programs by providing concurre...