Development of an approach to automatic test generation based on the graph model of a cache hierarchy

Verification of the cache hierarchy in modern SoCs due to the large state space requires a huge amount of complex tests. To cover the entire state space of the cache memory hierarchy graph model is proposed. The generation of tests based on this model, whose vertices (V) are the set of states (tags, values, etc.) of each cache and the edges (E) are the many transitions between states (instructions for reading, writing). Thus a graph model is constructed that describes all the states of the cache memory hierarchy. Each edge in the graph is a separate verification sequence. Vector-block operation with memory is provided. The approach described in the paper showed a good result when checking the hierarchy of the multiport cache memory of the developed kernel with the new vector VLIW DSP architecture, revealing several architectural and functional errors. Further, this approach will be applied to test other processor cores and their blocks