Modern architectures rely on memory fences to prevent undesired weakenings of memory consistency. As the fences’ semantics may be subtle, the automation of their placement is highly desirable. But precise methods for restoring consistency do not scale to deployed systems code. We choose to trade some precision for genuine scalability: our technique is suitable for large code bases. We implement it in our new musketeer tool, and report experiments on more than 700 executables from packages found in Debian GNU/Linux 7.1, including memcached with about 10,000 LoC
For efficiency reasons, most modern processor architectures allow the reordering of CPU instructions...
Computer architectures with weak memory models, such as ARMv8 and ARMv7, allow memory accesses to be...
Shared memory has been widely adopted as the primary system level programming abstraction on modern ...
Modern architectures rely on memory fences to prevent undesired weakenings of memory consistency. As...
Modern architectures rely on memory fences to prevent undesired weakenings of memory consistency. As...
Fences are instructions that programmers or compilers insert in the code to prevent the compiler or ...
Modern architectures provide weaker memory consistency guarantees than sequential consistency. These...
Modern architectures provide weaker memory consistency guarantees than sequential consistency. These...
Abstract. Modern architectures provide weaker memory consistency guarantees than sequential consiste...
Abstract—This paper addresses the problem of placing mem-ory fences in a concurrent program running ...
Memory fences inhibit the reordering of memory accesses in modern microprocessors; fences are useful...
Many modern multicore architectures support shared mem-ory for ease of programming and relaxed memor...
Abstract—We observe that fence instructions used by pro-grammers are usually only intended to order ...
Cache coherence protocols based on self-invalidation and self-downgrade haverecently seen increased ...
International audienceCache coherence protocols using self-invalidation and self-downgrade have rece...
For efficiency reasons, most modern processor architectures allow the reordering of CPU instructions...
Computer architectures with weak memory models, such as ARMv8 and ARMv7, allow memory accesses to be...
Shared memory has been widely adopted as the primary system level programming abstraction on modern ...
Modern architectures rely on memory fences to prevent undesired weakenings of memory consistency. As...
Modern architectures rely on memory fences to prevent undesired weakenings of memory consistency. As...
Fences are instructions that programmers or compilers insert in the code to prevent the compiler or ...
Modern architectures provide weaker memory consistency guarantees than sequential consistency. These...
Modern architectures provide weaker memory consistency guarantees than sequential consistency. These...
Abstract. Modern architectures provide weaker memory consistency guarantees than sequential consiste...
Abstract—This paper addresses the problem of placing mem-ory fences in a concurrent program running ...
Memory fences inhibit the reordering of memory accesses in modern microprocessors; fences are useful...
Many modern multicore architectures support shared mem-ory for ease of programming and relaxed memor...
Abstract—We observe that fence instructions used by pro-grammers are usually only intended to order ...
Cache coherence protocols based on self-invalidation and self-downgrade haverecently seen increased ...
International audienceCache coherence protocols using self-invalidation and self-downgrade have rece...
For efficiency reasons, most modern processor architectures allow the reordering of CPU instructions...
Computer architectures with weak memory models, such as ARMv8 and ARMv7, allow memory accesses to be...
Shared memory has been widely adopted as the primary system level programming abstraction on modern ...