The test of present integrated circuits exhibits many confining aspects, among them the adequate selection of the observable variables, the use of combined testing approaches, an each time more restricted controllability and observability (physically and electrically) and finally the required testing time. In the paper these points are discussed and different nowadays-promising techniques exposed. Complementarily to the logic output variable analysis (both value and delay) three efficient detection and localisation techniques can be considered that are contemplated in this work: the detection of light, heat and leakage currents due to the presence of failures. In most of the cases it is not possible to differentiate clearly, like was in the...
Knowing the root cause of why an Integrated Circuit (1C) device fails to function properly is the ke...
As CMOS technologies scale down, background leakage current increases inexorably, primarily due to ...
This paper presents a test technique that employs two different supply voltages for the same Iddq pa...
The test of present integrated circuits exhibits many confining aspects, among them the adequate sel...
With the advent of VLSI technology, the systems fabricated in deep sub micron technology are more pr...
With the advent of VLSI technology, the systems fabricated in deep sub micron technology are more pr...
With the increase in the complexity of the semiconductor device processes and increase in the challe...
With the increase in the complexity of the semiconductor device processes and increase in the challe...
Les dernières technologies comme la 65nm, 45nm et la nouvelle technologie 32nm qui sera disponible à...
With the increase in the complexity of the semiconductor device processes and increase in the challe...
Abstract—In this paper, we have proposed a new approach for optical failure analysis which employs a...
This thesis examines the impact of technology scaling, in the deep submicron regime, on the testabil...
A new data capturing technique for a potentially coupled bus of lines is proposed that always accomm...
A new data capturing technique for a potentially coupled bus of lines is proposed that always accomm...
The authors establish main guidelines of new methods and new tools which allows one to test for fail...
Knowing the root cause of why an Integrated Circuit (1C) device fails to function properly is the ke...
As CMOS technologies scale down, background leakage current increases inexorably, primarily due to ...
This paper presents a test technique that employs two different supply voltages for the same Iddq pa...
The test of present integrated circuits exhibits many confining aspects, among them the adequate sel...
With the advent of VLSI technology, the systems fabricated in deep sub micron technology are more pr...
With the advent of VLSI technology, the systems fabricated in deep sub micron technology are more pr...
With the increase in the complexity of the semiconductor device processes and increase in the challe...
With the increase in the complexity of the semiconductor device processes and increase in the challe...
Les dernières technologies comme la 65nm, 45nm et la nouvelle technologie 32nm qui sera disponible à...
With the increase in the complexity of the semiconductor device processes and increase in the challe...
Abstract—In this paper, we have proposed a new approach for optical failure analysis which employs a...
This thesis examines the impact of technology scaling, in the deep submicron regime, on the testabil...
A new data capturing technique for a potentially coupled bus of lines is proposed that always accomm...
A new data capturing technique for a potentially coupled bus of lines is proposed that always accomm...
The authors establish main guidelines of new methods and new tools which allows one to test for fail...
Knowing the root cause of why an Integrated Circuit (1C) device fails to function properly is the ke...
As CMOS technologies scale down, background leakage current increases inexorably, primarily due to ...
This paper presents a test technique that employs two different supply voltages for the same Iddq pa...