Current Testing Procedure for Deep Submicron Devices

This paper presents a test technique that employs two different supply voltages for the same Iddq pattern. The results of the two measurements are subtracted in order to eliminate the inherent subthreshold leakage. Summary of the experiment carried out on “System on a Chip ” (SOC) device build in 0.35m technology is also shown. These experiments proved that the method is effective in detecting failures not detectable with the single limit Iddq. 1