Add to ORKGOne of the main challenges of modern processor designs is the implementation of scalable and efficient mechanisms to detect memory access order violations as a result of out-of-order execution. Conventional structures performing this task are complex, inefficient and power-hungry. This fact has generated a large body of work on optimizing address-based memory disambiguation logic, namely the load-store queue. In this paper we review the most significant proposals in this research field, focusing on our own contributions.Facultad de Informátic
Feedback-directed optimization has developed into an increasingly important tool in designing optimi...
Abstract—As FPGAs continue to increase in size, it becomes increasingly feasible and desirable to bu...
The use of large instruction windows coupled with aggressive out-of order and prefetching capabiliti...
One of the main challenges of modern processor designs is the implementation of scalable and efficie...
In high-end processors, increasing the number of in-flight instructions can improve performance by o...
An efficient mechanism to track and enforce memory dependences is crucial to an out-of-order micropr...
This paper describes several methods for improving the scalability of memory disambiguation hardware...
International audienceMemory disambiguation mechanisms, coupled with load/store queues in out-of-ord...
With the help of the memory dependence predic-tor the instruction scheduler can speculatively issue ...
The load-store queue (LQ-SQ) of modem superscalar processors is responsible for keeping the order of...
Because they are based on large content-addressable memories, load-store queues (LSQs) present imple...
In most modern processor designs, the HW dedicated to store data and instructions (memory hierarchy)...
Multicore processors have emerged as a powerful platform on which to efficiently exploit thread-leve...
Feedback-directed optimization has developed into an increasingly important tool in designing optimi...
Modern out-of-order processor architectures focus significantly on the high performance execution of...
Feedback-directed optimization has developed into an increasingly important tool in designing optimi...
Abstract—As FPGAs continue to increase in size, it becomes increasingly feasible and desirable to bu...
The use of large instruction windows coupled with aggressive out-of order and prefetching capabiliti...
One of the main challenges of modern processor designs is the implementation of scalable and efficie...
In high-end processors, increasing the number of in-flight instructions can improve performance by o...
An efficient mechanism to track and enforce memory dependences is crucial to an out-of-order micropr...
This paper describes several methods for improving the scalability of memory disambiguation hardware...
International audienceMemory disambiguation mechanisms, coupled with load/store queues in out-of-ord...
With the help of the memory dependence predic-tor the instruction scheduler can speculatively issue ...
The load-store queue (LQ-SQ) of modem superscalar processors is responsible for keeping the order of...
Because they are based on large content-addressable memories, load-store queues (LSQs) present imple...
In most modern processor designs, the HW dedicated to store data and instructions (memory hierarchy)...
Multicore processors have emerged as a powerful platform on which to efficiently exploit thread-leve...
Feedback-directed optimization has developed into an increasingly important tool in designing optimi...
Modern out-of-order processor architectures focus significantly on the high performance execution of...
Feedback-directed optimization has developed into an increasingly important tool in designing optimi...
Abstract—As FPGAs continue to increase in size, it becomes increasingly feasible and desirable to bu...
The use of large instruction windows coupled with aggressive out-of order and prefetching capabiliti...