Dynamic memory disambiguation in the presence of out-of-order store issuing

With the help of the memory dependence predic-tor the instruction scheduler can speculatively issue load instructions at the earliest possible time without causing signicant amounts of memory order viola-tions. For maximum performance, the scheduler must also allow full out-of-order issuing of store instruc-tions since any super uous ordering of stores results in false memory dependencies which adversely af-fect the timely issuing of dependent loads. Unfortu-nately, simple techniques of detecting memory order violations do not work well when store instructions is-sue out-of-order since they yield many false memory order violations. By using a novel memory order vi-olation detection mechanism that is employed in the re-tire logic of the processor and delaying the checking for memory order violations, we are able to allow full out-of-order issuing of store instructions without causing false memory order violations. In addition, our mech-anism can take advantage of data value redundancy. We present an implementation of our technique using the store set memory dependence predictor. An out-of-order superscalar processor that uses our technique delivers an IPC which is within 100, 96 and 85 % of a processor equipped with an ideal memory disambiguator at issue widths of 8, 16 and 32 instructions respectively.