To improve the execution time of a program, parts of its instructions can be allocated to a fast Scratchpad Memory (SPM) at compile time. This is a well-known technique which can be used to minimize the program's worst-case Execution Time (WCET). However, modern embedded systems often use cached main memories. An SPM allocation will inevitably lead to changes in the program's memory layout in main memory, resulting in either improved or degraded worst-case caching behavior. We tackle this issue by proposing a cache-aware SPM allocation algorithm based on integer-linear programming which accounts for changes in the worst-case cache miss behavior
Caches are a source of unpredictability since it is very difficult to predict if a memory access res...
Truly incremental development is a holy grail of verification-intensive software industry. All facto...
In recent years, the real-time community has produced a variety of approaches targeted at managing o...
abstract: Cyber-physical systems and hard real-time systems have strict timing constraints that spec...
Over the past years, multicore systems emerged into the domain of hard real-time systems. These syst...
Abstract—This paper compares two proposed alternatives to conventional instruction caches: a scratch...
Cache memories have been extensively used to bridge the gap between high speed processors and relati...
In modern processor architectures, caches are widely used to shorten the gap between the processor s...
Embedded/Cyber-physical systems, have become popular in a wide range of application scenarios. Su...
In the embedded domain, the gap between memory and processor performance and the increase in applica...
ABSTRACT This paper presents the first memory allocation scheme for embedded systems having scratch-...
In the embedded domain, the gap between memory and processor performance and the increase in applica...
Abstract—Code repositioning is a well-known method of reducing inefficient off-chip memory accesses ...
In this research we propose a highly predictable, low overhead and yet dynamic, memory allocation st...
This paper presents the first memory allocation scheme for embedded systems having a scratch-pad mem...
Caches are a source of unpredictability since it is very difficult to predict if a memory access res...
Truly incremental development is a holy grail of verification-intensive software industry. All facto...
In recent years, the real-time community has produced a variety of approaches targeted at managing o...
abstract: Cyber-physical systems and hard real-time systems have strict timing constraints that spec...
Over the past years, multicore systems emerged into the domain of hard real-time systems. These syst...
Abstract—This paper compares two proposed alternatives to conventional instruction caches: a scratch...
Cache memories have been extensively used to bridge the gap between high speed processors and relati...
In modern processor architectures, caches are widely used to shorten the gap between the processor s...
Embedded/Cyber-physical systems, have become popular in a wide range of application scenarios. Su...
In the embedded domain, the gap between memory and processor performance and the increase in applica...
ABSTRACT This paper presents the first memory allocation scheme for embedded systems having scratch-...
In the embedded domain, the gap between memory and processor performance and the increase in applica...
Abstract—Code repositioning is a well-known method of reducing inefficient off-chip memory accesses ...
In this research we propose a highly predictable, low overhead and yet dynamic, memory allocation st...
This paper presents the first memory allocation scheme for embedded systems having a scratch-pad mem...
Caches are a source of unpredictability since it is very difficult to predict if a memory access res...
Truly incremental development is a holy grail of verification-intensive software industry. All facto...
In recent years, the real-time community has produced a variety of approaches targeted at managing o...