In this research we propose a highly predictable, low overhead and yet dynamic, memory allocation strategy for embedded systems with scratch-pad memory. A scratch-pad is a fast compiler-managed SRAM memory that replaces the hardware-managed cache. It is motivated by its better real-time guarantees vs cache and by its significantly lower overheads in energy consumption, area and overall runtime, even with a simple allocation scheme. Scratch-pad allocation primarily methods are of two types. First, software-caching schemes emulate the workings of a hardware cache in software. Instructions are inserted before each load/store to check the softwaremaintained cache tags. Such methods incur large overheads in runtime, code size, energy consumption...
In order to meet the requirements concerning both performance and energy consumption in embedded sy...
Abstract—Exploiting runtime memory access traces can be a complementary approach to compiler optimiz...
Nowadays, many embedded processors include in their architecture on-chip static memories, so called ...
In this research we propose a highly predictable, low overhead and yet dynamic, memory allocation s...
In this research we propose a highly predictable, low overhead and yet dynamic, memory allocation st...
ABSTRACT This paper presents the first memory allocation scheme for embedded systems having scratch-...
<p>An increasing number of processor architectures support scratch-pad memory - software manag...
Many embedded systems feature processors coupled with a small and fast scratchpad memory. To the dif...
This thesis presents the first-ever compile-time method for allocating a portion of a program’s dyna...
ABSTRACT This paper presents the first automatic scheme to allocate local (stack) data in recursive ...
This thesis presents the first-ever compile-time method for allocating a portion of a program's dyna...
This paper presents the first memory allocation scheme for embedded systems having a scratch-pad mem...
This paper presents a dynamic scratchpad memory (SPM) code allocation technique for embedded systems...
Efficient utilization of on-chip memory space is extremely important in modern embedded system appli...
Efficient utilization of on-chip memory space is extremely important in modern embedded system appli...
In order to meet the requirements concerning both performance and energy consumption in embedded sy...
Abstract—Exploiting runtime memory access traces can be a complementary approach to compiler optimiz...
Nowadays, many embedded processors include in their architecture on-chip static memories, so called ...
In this research we propose a highly predictable, low overhead and yet dynamic, memory allocation s...
In this research we propose a highly predictable, low overhead and yet dynamic, memory allocation st...
ABSTRACT This paper presents the first memory allocation scheme for embedded systems having scratch-...
<p>An increasing number of processor architectures support scratch-pad memory - software manag...
Many embedded systems feature processors coupled with a small and fast scratchpad memory. To the dif...
This thesis presents the first-ever compile-time method for allocating a portion of a program’s dyna...
ABSTRACT This paper presents the first automatic scheme to allocate local (stack) data in recursive ...
This thesis presents the first-ever compile-time method for allocating a portion of a program's dyna...
This paper presents the first memory allocation scheme for embedded systems having a scratch-pad mem...
This paper presents a dynamic scratchpad memory (SPM) code allocation technique for embedded systems...
Efficient utilization of on-chip memory space is extremely important in modern embedded system appli...
Efficient utilization of on-chip memory space is extremely important in modern embedded system appli...
In order to meet the requirements concerning both performance and energy consumption in embedded sy...
Abstract—Exploiting runtime memory access traces can be a complementary approach to compiler optimiz...
Nowadays, many embedded processors include in their architecture on-chip static memories, so called ...