WCET-centric software-controlled instruction caches for hard real-time systems

Cache memories have been extensively used to bridge the gap between high speed processors and relatively slower main memories. However, they are sources of pre-dictability problems because of their dynamic and adaptive behavior, and thus need special attention to be used in hard real-time systems. A lot of progress has been achieved in the last ten years to statically predict worst-case execution times (WCETs) of tasks on architectures with caches. How-ever, cache-aware WCET analysis techniques are not al-ways applicable due to the lack of documentation of hard-ware manuals concerning the cache replacement policies. Moreover, they tend to be pessimistic with some cache re-placement policies (e.g. random replacement policies) [6]. Lastly, caches are sources of timing anomalies in dynami-cally scheduled processors [13] (a cache miss may in some cases result in a shorter execution time than a hit). To reconciliate performance and predictability of caches, we propose in this paper algorithms for software control of instruction caches. The proposed algorithms stat-ically divide the code of tasks into regions, for which the cache contents is statically selected. At run-time, at ev-ery transition between regions, the cache contents computed off-line is loaded into the cache and the cache replacement policy is disabled (the cache is locked). Experimental re-sults provided in the paper show that with an appropriate selection of regions and cache contents, the worst-case per-formance of applications with locked instruction caches is competitive with the worst-case performance of unlocked caches.