Run-time reconfigurable logic is an interesting design alterative in SoC design because it can simultaneously provide high performance and flexibility. However, its configuration overhead can largely decrease the system performance. In this work, we present a novel configuration locking technique to reduce the overhead. The idea is to lock at run-time a number of frequently used tasks on the configuration memory so that they cannot be evicted by other tasks. A number of real applications were used to validate the approach. The results show that using proper amount of resources to lock frequently used tasks can significantly improve the performance
Runtime reconfiguration provides an efficient means to reduce the hardware cost, while satisfying th...
In spite of the increasing success of reconfigurable hardware, the dynamic reconfiguration can intro...
Dynamic FPGA reconfiguration represents an overhead that can be critical to the performance of a rea...
Run-time reconfigurable logic is an interesting design alterative in SoC design because it can simul...
Run-time reconfigurable logic is a very attractive alterative in the design of SoC. However, configu...
Dynamically reconfigurable hardware (DRHW) not only has high silicon reusability, but it can also de...
This work presents a novel run-time reconfiguration model. It uses multiple configuration controller...
Runtime reconfigurable systems built upon devices with partial reconfiguration can provide reduction...
Multitasking on reconfigurable logic can achieve very high silicon reusability. However, configurati...
Dynamically reconfigurable systems based on partial and dynamically reconfigurable FPGAs may have t...
The efficiency of the reconfiguration process in modern FPGAs can improve drastically if an on-chip ...
Dynamically reconfigurable logic is becoming an important design unit in SoC system. A method to mak...
In this paper, an approach that uses dynamic voltage scaling (DVS) to reduce the configuration energ...
Dynamically reconfigurable hardware is a promising technology that combines in the same device both ...
Runtime reconfiguration is a promising solution for reducing hardware cost in embedded systems, with...
Runtime reconfiguration provides an efficient means to reduce the hardware cost, while satisfying th...
In spite of the increasing success of reconfigurable hardware, the dynamic reconfiguration can intro...
Dynamic FPGA reconfiguration represents an overhead that can be critical to the performance of a rea...
Run-time reconfigurable logic is an interesting design alterative in SoC design because it can simul...
Run-time reconfigurable logic is a very attractive alterative in the design of SoC. However, configu...
Dynamically reconfigurable hardware (DRHW) not only has high silicon reusability, but it can also de...
This work presents a novel run-time reconfiguration model. It uses multiple configuration controller...
Runtime reconfigurable systems built upon devices with partial reconfiguration can provide reduction...
Multitasking on reconfigurable logic can achieve very high silicon reusability. However, configurati...
Dynamically reconfigurable systems based on partial and dynamically reconfigurable FPGAs may have t...
The efficiency of the reconfiguration process in modern FPGAs can improve drastically if an on-chip ...
Dynamically reconfigurable logic is becoming an important design unit in SoC system. A method to mak...
In this paper, an approach that uses dynamic voltage scaling (DVS) to reduce the configuration energ...
Dynamically reconfigurable hardware is a promising technology that combines in the same device both ...
Runtime reconfiguration is a promising solution for reducing hardware cost in embedded systems, with...
Runtime reconfiguration provides an efficient means to reduce the hardware cost, while satisfying th...
In spite of the increasing success of reconfigurable hardware, the dynamic reconfiguration can intro...
Dynamic FPGA reconfiguration represents an overhead that can be critical to the performance of a rea...