Run-time reconfigurable logic is a very attractive alterative in the design of SoC. However, configuration overhead can largely decrease the system performance. In this work, we present a novel configuration locking technique to reduce the effect of the overhead. The idea is to at run-time lock a number of the most frequently used tasks on the configuration memory so that they cannot be evicted by other tasks. With real applications in validation, the results show that using proper amount of resources to lock tasks can significantly outperform simply using more resources. In addition, an algorithm has been developed for estimating the lock ratio. Experimental results show that the estimates are close to optimal results and the measured comp...
The efficiency of the reconfiguration process in modern FPGAs can improve drastically if an on-chip ...
New generation embedded systems demand high performance, efficiency and flexibility. Reconfigurable ...
The increasing popularity of multi-core System-on-Chip platforms introduces new challenges, both in ...
Run-time reconfigurable logic is a very attractive alterative in the design of SoC. However, configu...
Run-time reconfigurable logic is an interesting design alterative in SoC design because it can simul...
Dynamically reconfigurable hardware (DRHW) not only has high silicon reusability, but it can also de...
Runtime reconfigurable systems built upon devices with partial reconfiguration can provide reduction...
This work presents a novel run-time reconfiguration model. It uses multiple configuration controller...
Runtime reconfiguration provides an efficient means to reduce the hardware cost, while satisfying th...
Cache memories in embedded systems play an important role in reducing the execution time of the appl...
Abstract—In recent years, cache locking have appeared as a solution to ease the schedulability analy...
Runtime reconfiguration is a promising solution for reducing hardware cost in embedded systems, with...
Multitasking on reconfigurable logic can achieve very high silicon reusability. However, configurati...
Many desired features of computing platforms, such as increased fault tolerance, variable quality of...
Embedded systems are becoming increasingly common in everyday life and like their general-purpose co...
The efficiency of the reconfiguration process in modern FPGAs can improve drastically if an on-chip ...
New generation embedded systems demand high performance, efficiency and flexibility. Reconfigurable ...
The increasing popularity of multi-core System-on-Chip platforms introduces new challenges, both in ...
Run-time reconfigurable logic is a very attractive alterative in the design of SoC. However, configu...
Run-time reconfigurable logic is an interesting design alterative in SoC design because it can simul...
Dynamically reconfigurable hardware (DRHW) not only has high silicon reusability, but it can also de...
Runtime reconfigurable systems built upon devices with partial reconfiguration can provide reduction...
This work presents a novel run-time reconfiguration model. It uses multiple configuration controller...
Runtime reconfiguration provides an efficient means to reduce the hardware cost, while satisfying th...
Cache memories in embedded systems play an important role in reducing the execution time of the appl...
Abstract—In recent years, cache locking have appeared as a solution to ease the schedulability analy...
Runtime reconfiguration is a promising solution for reducing hardware cost in embedded systems, with...
Multitasking on reconfigurable logic can achieve very high silicon reusability. However, configurati...
Many desired features of computing platforms, such as increased fault tolerance, variable quality of...
Embedded systems are becoming increasingly common in everyday life and like their general-purpose co...
The efficiency of the reconfiguration process in modern FPGAs can improve drastically if an on-chip ...
New generation embedded systems demand high performance, efficiency and flexibility. Reconfigurable ...
The increasing popularity of multi-core System-on-Chip platforms introduces new challenges, both in ...