Testing and Fault-Tolerance Aspects of High-Density VLSI Memory

105 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1988.Presented in this thesis is a design strategy for efficient and comprehensive parallel testing of both Random Access Memory (RAM) and Content Addressable Memory (CAM). Based on this design for testability approach, parallel testing algorithms for RAMs and CAMs are developed for a broad class of parametric and pattern sensitive faults. The resulting test procedures are significantly more efficient than previous approaches. For example, the design for the testability strategy allows an entire w word CAM to be read in just one operation with a resulting speed-up in testing as high as w. In the case of an n bit RAM, the improvement in test efficiency of the proposed algorithms is by a factor of $O(\sqrt{n})$. Concepts of planar tessellation and graph theory have been employed to design optimal test algorithms. In embedded applications, where neither the address and read/write lines are externally controllable nor are the output lines directly observable, the proposed algorithms have been adapted for Built-In Self-Test (BIST) implementation. It is also shown that the proposed design for testability is amenable to random testing in the event BIST hardware cannot be integrated at the site of the memory. Markov chain analysis has been made to estimate the detection quality and fault coverage for test length of different sizes.Also the on-line fault detection and correction due to alpha-particle-induced soft error and other transients, have been investigated. Three different types of coding have been proposed to correct as many as two errors per word line and 2$\sqrt{n}$ errors per memory chip of size n bits. The proposed coding is thus useful for Three Dimensional Dynamic Random Access Memory (3D DRAM), where the storage capacitors are vertically mounted in close proximity, and thereby double errors per word line are common. Reliability analysis has been made, and it has been shown that the reliability improvement due to proposed techniques is by a factor of 10$\sp6$. Finally, it has been demonstrated how to integrate the concepts of testability and fault-tolerance within a chip so that during normal operation the testable logic can be reconfigured into an error-correcting circuit.U of I OnlyRestricted to the U of I community idenfinitely during batch ingest of legacy ETD