Self-Testing Vlsi Circuits (Built-In, Fault Detection, Dynamic Ram, Design).

A self-testing circuit design methodology is developed for off-line testing of regular or nearly regular VLSI (very large scale integrated) circuits. It is based on four major design concepts: circuit partitioning, regularization to produce identical subcircuits (partitions), parallel testing of partitions, and fault detection by direct comparison of response streams from the partitions. Existing concepts of regular circuits (iterative logic arrays) are generalized to include array-like circuits that contain several cell types and are moderately irregular. A heuristic circuit partitioning and regularization method based on subcircuit isomorphism is introduced. An on-chip test generation technique employing non-linear feedback shift registers is developed to generate test pattern sequences with very high fault coverage. A new way of designing the feedback shift registers is presented which greatly reduces the complexity of the feedback circuits and the number of redundant test patterns. An efficient MOS equality checker is defined that can compare a large number of parallel response streams. The proposed design methodology is applied to the problem of making very large dynamic r and om access memory (RAM) chips self-testing. Such RAMS are the most widely used VLSI circuits. The physical failure modes, including the difficult neighborhood interference faults, of a typical dynamic RAM are analyzed to identify their testing needs. From these, a comprehensive test generation algorithm suitable for on-chip implementation is developed. The storage cell arrays found in conventional RAM layouts are treated as partitions for testing purposes. Their peripheral circuits are modified so that the partitions can be tested in parallel. Within each partition, many storage cells are tested simultaneously using a special shifting operation, which requires minor modification to the st and ard sense amplifier arrays. Other peripheral circuits are also redesigned to facilitate test application and response verification. It is shown that the testing time of a self-testing RAM is much less than that of conventional designs that use external testing. The chip area overhead is also small, and decreases as a percentage of the total chip area as RAM capacity increases. Extension of the proposed methods to static RAM design is also discussed.PhDElectrical engineeringUniversity of Michiganhttp://deepblue.lib.umich.edu/bitstream/2027.42/161055/1/8612659.pd