Journal ArticleSelf-timed systems structured as multiple concurrent processes and communicating through self-timed queues are a convenient way to implement decoupled computer architectures. Machines of this type can exploit instruction level parallelism in a natural way, and can be easily modified and extended. However, providing a precise exception model for a self-timed micropipelined processor can be difficult, since the processor state does not change at uniformly discrete intervals. We present a precise exception method implemented for Fred, a self-timed, decoupled, pipelined computer architecture with out-of-order instruction completion
The major bottleneck in today’s pipelined microprocessors has been data dependencies and branch pred...
We argue that at least for embedded software applications, computer architecture, software, and netw...
Journal ArticleAsynchronous or self-timed systems that do not rely on U global clock to keep system...
Journal ArticleDecoupled computer architectures provide an effective means of exploiting instructio...
The design of an exception handling mechanism for communicating sequential processes is presented. I...
This paper argues that repeatable timing is more important and more achievable than predictable timi...
Abstract—Embedded systems have higher requirements on real-time performance of processor. However ex...
Clocked (synchronous) and self-timed (asynchronous) represent the two prinicipal methodologies assoc...
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer...
Early prediction of an upcoming timing violation presents a tremendous opportunity to mask the perfo...
In complex System-on-a-Chip (SoC) designs, designers often need to add new features into an original...
Certain hard real-time tasks demand precise timing of events, but the usual software solution of per...
Journal ArticleThe NSR (Non-Synchronous RISC) processor is a general-purpose computer structured (I...
Abstract—Interrupt behaviors, particularly the external ones, are difficult to verify in a microproc...
Journal ArticleSelf- timed circuits offer advantages over their synchronously clocked counterparts i...
The major bottleneck in today’s pipelined microprocessors has been data dependencies and branch pred...
We argue that at least for embedded software applications, computer architecture, software, and netw...
Journal ArticleAsynchronous or self-timed systems that do not rely on U global clock to keep system...
Journal ArticleDecoupled computer architectures provide an effective means of exploiting instructio...
The design of an exception handling mechanism for communicating sequential processes is presented. I...
This paper argues that repeatable timing is more important and more achievable than predictable timi...
Abstract—Embedded systems have higher requirements on real-time performance of processor. However ex...
Clocked (synchronous) and self-timed (asynchronous) represent the two prinicipal methodologies assoc...
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer...
Early prediction of an upcoming timing violation presents a tremendous opportunity to mask the perfo...
In complex System-on-a-Chip (SoC) designs, designers often need to add new features into an original...
Certain hard real-time tasks demand precise timing of events, but the usual software solution of per...
Journal ArticleThe NSR (Non-Synchronous RISC) processor is a general-purpose computer structured (I...
Abstract—Interrupt behaviors, particularly the external ones, are difficult to verify in a microproc...
Journal ArticleSelf- timed circuits offer advantages over their synchronously clocked counterparts i...
The major bottleneck in today’s pipelined microprocessors has been data dependencies and branch pred...
We argue that at least for embedded software applications, computer architecture, software, and netw...
Journal ArticleAsynchronous or self-timed systems that do not rely on U global clock to keep system...