OUT-OF-ORDER COMMIT LOGIC WITH PRECISE EXCEPTION HANDLING FOR PIPELINED PROCESSORS

The major bottleneck in today’s pipelined microprocessors has been data dependencies and branch prediction. Existing approaches have focused on issuing instructions out-of-order but have limited themselves to committing in-order considering the amount of overhead involved. This paper proposes an architecture in which instructions are allowed to commit out-of-order thereby increasing the throughput. The problem of precise exception handling in out-of-order commit has also been handled without involving significant hardware overhead. The design proposed in this paper can also be extended in future to incorporate branch prediction