Level-one data cache (L1 DC) and data translation lookaside buffer (DTLB) accesses impact energy usage as they frequently occur and each L1 DC and DTLB access uses significantly more energy than a register file access. Often, multiple memory operations will reference the same cache line using the same register, such as when iterating through an array. We propose to memoize L1 DC access information, such as the L1 DC data array way and the DTLB way, by associating this information with the register used to access it. When a load or store calculates the memory address, we detect whether the calculated address shares the cache line memoized with the base register. If so, we avoid the L1 DC tag array access and the DTLB access to determine the ...
Energy efficiency is a first-order design goal for nearly all classes of processors, but it is parti...
High-performance processors use a large set–associative L1 data cache with multiple ports. As clock ...
In recent years, CPU performance has become energy constrained. If performance is to continue increa...
Level-one data cache (L1 DC) and data translation lookaside buffer (DTLB) accesses impact energy usa...
Level-one data cache (L1 DC) accesses impact energy usage as they frequently occur and use significa...
Memory operations have a significant impact on both performance and energy usage even when an access...
The number of battery powered devices is growing significantly and these devices require energy-effi...
The need for energy efficiency continues to grow for many classes of processors, including those for...
Energy efficiency is one of the key metrics in the design of a widerange of processor types. For exa...
Abstract—Fast set-associative level-one data caches (L1 DCs) access all ways in parallel during load...
Fast set-associative level-one data caches (L1 DCs) access all ways in parallel during load operatio...
Abstract—Fast set-associative level-one data caches (L1 DCs) access all ways in parallel during load...
Due to performance reasons, all ways in set-associative level-one (L1) data caches are accessed in p...
Abstract—Due to performance reasons, all ways in set-associative level-one (L1) data caches are acce...
As CPU data requests to the level-one (L1) data cache (DC) can represent as much as 25 % of an embed...
Energy efficiency is a first-order design goal for nearly all classes of processors, but it is parti...
High-performance processors use a large set–associative L1 data cache with multiple ports. As clock ...
In recent years, CPU performance has become energy constrained. If performance is to continue increa...
Level-one data cache (L1 DC) and data translation lookaside buffer (DTLB) accesses impact energy usa...
Level-one data cache (L1 DC) accesses impact energy usage as they frequently occur and use significa...
Memory operations have a significant impact on both performance and energy usage even when an access...
The number of battery powered devices is growing significantly and these devices require energy-effi...
The need for energy efficiency continues to grow for many classes of processors, including those for...
Energy efficiency is one of the key metrics in the design of a widerange of processor types. For exa...
Abstract—Fast set-associative level-one data caches (L1 DCs) access all ways in parallel during load...
Fast set-associative level-one data caches (L1 DCs) access all ways in parallel during load operatio...
Abstract—Fast set-associative level-one data caches (L1 DCs) access all ways in parallel during load...
Due to performance reasons, all ways in set-associative level-one (L1) data caches are accessed in p...
Abstract—Due to performance reasons, all ways in set-associative level-one (L1) data caches are acce...
As CPU data requests to the level-one (L1) data cache (DC) can represent as much as 25 % of an embed...
Energy efficiency is a first-order design goal for nearly all classes of processors, but it is parti...
High-performance processors use a large set–associative L1 data cache with multiple ports. As clock ...
In recent years, CPU performance has become energy constrained. If performance is to continue increa...