Data Access Techniques for Enhanced Energy Efficiency and Performance in In-order Pipelines

Energy efficiency is one of the key metrics in the design of a widerange of processor types. For example, battery powered devices, whichare growing in numbers every day, require energy efficient processorsto be able to operate for a useful period of time. Techniques thatimproves the energy efficiency of a processor can alleviate theproblems like heat generation to a certain level which in turn canallow to achieve better performance. In addition, energy efficiencyreduces the operating costs of high performance computing systemswhich is very desirable.Level-1 data caches (L1 DC) dissipate a significant portion of thepipeline energy in general purpose processors. For example, L1 DC candissipate up to 23% of the pipeline energy in a 7-stage single-issuein-order pipeline. In this thesis, a number of techniques areintroduced in order to reduce the energy dissipation of L1 DCs. Focusis given to reduce the L1 DC energy without reducing the performance,since L1 DC accesses affect the performance of the processor. Some ofthe techniques introduced in this thesis can even improve the performanceof the processor slightly. In addition, the ease of implementation is oneof the important considerations in this thesis, in which the energysaving techniques should be able implementable with the commonsemi-custom design flows. Some of the proposedtechniques reduce the energy dissipation of data translationlookaside buffer (DTLB) which is closely coupled with L1 DC.Two of the papers that are included in this thesis, that is,Speculative Tag Access (STA) and Early Load Data Dependence Detection(ELD^3) are very simple to implement in order toreduce the L1 DC access energy. Another Two papers are included in thethesis are about filter caches, but the main focus is given to theData Filter Cache (DFC). The first paper tackles the implementationissues related to previously proposed data filter caches and proposesnovel ways to utilize DFC in the pipeline to reduce the energydissipation of both L1 DC and DTLB, but also improve the performanceat the same time. The second paper, utilizes filter caches forwide-voltage-range processors in order to tackle the issue ofscalability problems of SRAMs used in level-1 caches. A paper abouthardware/software co-design technique is introduced to evaluate thepotential of software control on the energy efficiency of L1 DCaccesses. In the final paper that is included in the thesis, a 7-stagepipeline is evaluated in detail in terms of execute stage and L1 DCaccess stage which affect the performance directly due to datadependencies