On the interaction between power-aware computer-aided design algorithms for field-programmable gate arrays

As Field Programmable Gate Array (FPGA) power consumption continues to increase, lower power FPGA circuitry, architectures, and Computer-Aided Design (CAD) tools need to be developed. Before designing low-power FPGA circuitry, architectures, or CAD tools, we must first determine where the biggest gains (in terms of energy reduction) are to be made and whether these gains are cumulative. In this thesis, we focus on FPGA CAD tools. Specifically, we describe a new power-aware CAD flow for FPGAs that was developed to answer the above questions. Estimating energy using very detailed post-route power and delay models, we determine the gains obtained by our power-aware technology mapping, clustering, placement, and routing algorithms and investigate how each gain behaves when the algorithms are applied concurrently. The individual energy reductions of the power-aware technology-mapping, clustering, placement, and routing algorithms were 7.6%, 12.6%, 3.0%, and 2.6% respectively. The majority of the overall energy reduction was achieved during the technology mapping and clustering stages of the power-aware FPGA CAD flow. In addition, the gains were mostly cumulative when the individual power-aware CAD algorithms were applied concurrently with overall energy reductions of 22.6%.Applied Science, Faculty ofElectrical and Computer Engineering, Department ofGraduat