FPGA architectures and CAD algorithms with dynamic power gating support

As the CMOS technology scales down, the cost of fabricating an integrated circuit becomes more expensive. Field-programmable gate arrays (FPGAs) are becoming attractive because their fabrication costs are amortized among many customers. A major challenge that face adopting FPGAs in many low-power applications is their high power consumption due to their reconfigurablity. A significant portion of FPGAs' power is dissipated in the form of static power during applications' idle periods. To address the power challenge in FPGAs, this dissertation proposes architecture enhancements and algorithms support to enable powering down portions of a chip during their idle times using power gating. This leads to significant energy savings especially for applications with long idle periods, such as mobile devices. This dissertation presents three contributions that address the major challenges in adopting power gating in FPGAs. The first contribution proposes an architectural support for power gating in FPGAs. This architecture enables powering down unused FPGA resources at configuration time, and powering down inactive resources during their idle times by the help of a controller. The controller can be placed on the general fabric of an FPGA device. The proposed architecture provides flexibility in realizing varying numbers and structures of modules that can be powered down at run-time when inactive. The second contribution proposes an architecture to appropriately handle the wakeup phase of power-gated modules. During a wakeup phase, a large current is drawn from the power supply to recharge the internal capacitances of a power-gated module, leading to reduced noise margins and degraded performance for neighbouring logic. The proposed architecture staggers the wakeup phase to limit this current to a safe level. This architecture is configurable and flexible to enable realizing different user applications, while having negligible area and power overheads and fast power up times. The third contribution proposes a CAD flow that supports mapping users' circuits to the proposed architecture. Enhancements to the algorithms in this flow that reduce power consumption are studied and evaluated. Furthermore, the CAD flow is used to study the granularity of the architecture proposed in this dissertation when mapping application circuits.Applied Science, Faculty ofElectrical and Computer Engineering, Department ofGraduat