Sequential Circuit Test Generation in a Genetic Algorithm Framework

Abstract|Test generation using deterministic faultoriented algorithms is highly complex and time-consuming. New approaches are needed to augment the existing techniques, both to reduce execution time and to improve fault coverage. In this work, we describe a genetic algorithm (GA) framework for sequential circuit test generation. The GA evolves candidate test vectors and sequences, using a fault simulator to compute the tness of each candidate test. Various GA parameters are studied, including alphabet size, tness function, generation gap, population size, and mutation rate, as well as selection and crossover schemes. High fault coverages were obtained for most of the IS-CAS89 sequential benchmark circuits, and execution times were signi cantly lower than in a deterministic test generator in most cases.