ABSTRACT Towards pB +-trees in the Field: Implementation Choices and Performance

In recent years the relative speed difference between CPUs and main-memory has become so great that many applications, including database management systems, spend much of their time waiting for data to be delivered from mainmemory. In particular, B +-trees have been shown to utilize cache memory poorly, triggering the development of many cache-conscious indices. While early studies of cacheconscious indices used simulation models, the trend has recently swung towards performance measurements on actual computer architectures. This paper is part of this trend towards the deployment of cache-conscious structures “in thefield”. WestudytheperformanceofthepB +-tree on the Itanium 2 processor, focusing on various implementation choices and their effect on performance. 1