In recent years the relative speed difference between CPUs and main-memory has become so great that many applications, including database management systems, spend much of their time waiting for data to be delivered from main-memory. In particular, B+-trees have been shown to utilize cache memory poorly, triggering the development of many cache-conscious indices. While early studies of cache-conscious indices used simulation models, the trend has recently swung towards performance measurements on actual computer architectures. This thesis is part of this trend towards the deployment of cache-conscious structures “in the field”. We study the performance of the pB+-tree on the Itanium 2 processor, focusing on various implementation choices an...
We have conducted a performance analysis of a large scale multiprocessor system based on shared buse...
As memory access times grow larger relative to processor cycle times, the cache performance of algor...
In this paper, we propose several different data and instruction cache configurations and analyze th...
In recent years the relative speed difference between CPUs and main-memory has be-come so great that...
In recent years the relative speed difference between CPUs and main-memory has become so great that ...
In main-memory databases, the number of processor cache misses has a critical impact on the performa...
In main-memory databases, the number of processor cache misses has a critical impact on the performa...
Recent research shows that the database performance can be significantly improved by the effective c...
B+-Trees have been traditionally optimized for I/O performance with disk pages as tree nodes. Recent...
B+-Trees have been traditionally optimized for I/O performance with disk pages as tree nodes. Recent...
Abstract. Researchers have modified existing index structures into ones opti-mized for CPU cache per...
Over the past few years, various indexes have been redesigned for byte-addressable persistent memory...
Many systems rely on optimistic concurrent search trees for multi-core scalability. In principle, op...
A new performance model of the memory hierarchy is first introduced, which describes all possible sc...
During the last two decades, computer hardware has experienced remarkable developments. Especially C...
We have conducted a performance analysis of a large scale multiprocessor system based on shared buse...
As memory access times grow larger relative to processor cycle times, the cache performance of algor...
In this paper, we propose several different data and instruction cache configurations and analyze th...
In recent years the relative speed difference between CPUs and main-memory has be-come so great that...
In recent years the relative speed difference between CPUs and main-memory has become so great that ...
In main-memory databases, the number of processor cache misses has a critical impact on the performa...
In main-memory databases, the number of processor cache misses has a critical impact on the performa...
Recent research shows that the database performance can be significantly improved by the effective c...
B+-Trees have been traditionally optimized for I/O performance with disk pages as tree nodes. Recent...
B+-Trees have been traditionally optimized for I/O performance with disk pages as tree nodes. Recent...
Abstract. Researchers have modified existing index structures into ones opti-mized for CPU cache per...
Over the past few years, various indexes have been redesigned for byte-addressable persistent memory...
Many systems rely on optimistic concurrent search trees for multi-core scalability. In principle, op...
A new performance model of the memory hierarchy is first introduced, which describes all possible sc...
During the last two decades, computer hardware has experienced remarkable developments. Especially C...
We have conducted a performance analysis of a large scale multiprocessor system based on shared buse...
As memory access times grow larger relative to processor cycle times, the cache performance of algor...
In this paper, we propose several different data and instruction cache configurations and analyze th...