PRACTICAL PERFORMANCE CONSIDERATIONS FOR THE PREFETCHING B+-TREE

In recent years the relative speed difference between CPUs and main-memory has be-come so great that many applications, including database management systems, spend much of their time waiting for data to be delivered from main-memory. In particular, B+-trees have been shown to utilize cache memory poorly, triggering the development of many cache-conscious indices. While early studies of cache-conscious indices used simulation models, the trend has recently swung towards performance measurements on actual computer architectures. This thesis is part of this trend towards the deployment of cache-conscious structures “in the field”. We study the performance of the pB+-tree on the Itanium 2 processor, focusing on various implementation choices and their effect on performance