HeDGE: Hybrid Dataflow Graph Execution in the Issue logic

IBM Technical Contact: Frank O’Connell Exposing more instruction-level parallelism in out-of-order superscalars requires increasing the number of dynamic instructions in flight. However, large instruction windows increase power consumption and latency in the issue logic. This latency limits clock speed. We propose a design called Hybrid Dataflow Graph Execution (HeDGE) for conventional Instruction Set Architectures (ISAs). HeDGE explicitly maintains dependences between instructions in the issue window by modifying the issue, register renaming, and wakeup logic. The HeDGE wakeup logic notifies only consumer instructions when data values arrive. Explicit consumer encoding naturally leads to the use of Random Addressable Memory (RAM) instead of Content Addressable Memory (CAM) needed for broadcast. HeDGE is distinguished from prior approaches in part because it dynamically inserts forwarding instructions. Although these additional instructions degrade performance by an average of 3 to 17 % for SPEC benchmarks and 1.5 % to 8 % for DaCapo benchmarks, they enable energy efficient execution in large instruction windows. The HeDGE RAM based instruction window consumes on average 98 % less energy than a conventional CAM as modeled in CACTI for 70nm technology. In conventional designs, this structure contributes 7 to 20 % to total energy consumption. Assuming a conservative 10 % contribution, HeDGE configurations reduce total processor energy by an average of 6%.