Timing-driven Partitioning and Timing Optimization of Mixed Static-Domino Implementations

Domino logic is a circuit family that is wellsuited to implementing high-speed circuits. Synthesis of domino circuits is more complex than static logic synthesis due to the non-inverting nature of the logic and the complex timing relationships associated with the clockscheme. In this paper, we address several problems along a domino synthesis ow. We mainly consider the problem of partitioning a circuit into static and domino regions under timing constraints. The algorithm is extended to develop a method for partitioning domino logic into two phases, with inverters permitted between the two phases, and then to a ow for general two-phase static-domino partitioning. We also address a timing veri cation and sizing optimization tool for circuits containing mixed domino and static logic