Add to ORKGAbstract — Two methods are presented for static timing verification of sequential circuits implemented as a mix of static and domino logic. Constraints for proper operation of domino gates are derived. An important observa-tion is that input signals to domino gates may start changing near the end of the evaluate phase. The first method models domino gates explicitly, similar to latches. The second method treats domino gates only during pre- and post-processing steps. This method is shown to be more conservative, but easier to compute.
As cycle time of chips shrinks and die size grows, clock skew measured as a fraction of the cycle ti...
A domino logic test circuit includes a dynamic node, a precharge device for charging the dynamic nod...
This dissertation discusses the overhead of traditional domino logic that consumes a higher cycle ti...
Two methods are presented for static timing verifica-tion of sequential circuits implemented as a mi...
This paper addresses static timing verification for sequential circuits implemented in a mix of stat...
Abstract — This paper addresses static timing verification for sequential circuits implemented in a ...
Domino logic is a circuit family that is wellsuited to implementing high-speed circuits. Synthesis o...
Domino logic is a high-performance circuit configuration that is usually embedded in static logic en...
Domino logic is a high-performance circuit configuration that is usually embedded in static logic en...
One of the challenges of high speed digital circuit design has been to achieve timing closure. With ...
One of the challenges of high speed digital circuit design has been to achieve timing closure. With ...
Abstract—Domino circuits are widely used in high-performance CMOS microprocessors. However, textbook...
This paper discusses the application of the timing analysis tool ATACS to the high performance, self...
Most digital systems are constructed using static CMOS logic and edge-triggered flip-flops. Although...
Abstract: Reduction of propagation delay is very important for high speed applications. This paper g...
As cycle time of chips shrinks and die size grows, clock skew measured as a fraction of the cycle ti...
A domino logic test circuit includes a dynamic node, a precharge device for charging the dynamic nod...
This dissertation discusses the overhead of traditional domino logic that consumes a higher cycle ti...
Two methods are presented for static timing verifica-tion of sequential circuits implemented as a mi...
This paper addresses static timing verification for sequential circuits implemented in a mix of stat...
Abstract — This paper addresses static timing verification for sequential circuits implemented in a ...
Domino logic is a circuit family that is wellsuited to implementing high-speed circuits. Synthesis o...
Domino logic is a high-performance circuit configuration that is usually embedded in static logic en...
Domino logic is a high-performance circuit configuration that is usually embedded in static logic en...
One of the challenges of high speed digital circuit design has been to achieve timing closure. With ...
One of the challenges of high speed digital circuit design has been to achieve timing closure. With ...
Abstract—Domino circuits are widely used in high-performance CMOS microprocessors. However, textbook...
This paper discusses the application of the timing analysis tool ATACS to the high performance, self...
Most digital systems are constructed using static CMOS logic and edge-triggered flip-flops. Although...
Abstract: Reduction of propagation delay is very important for high speed applications. This paper g...
As cycle time of chips shrinks and die size grows, clock skew measured as a fraction of the cycle ti...
A domino logic test circuit includes a dynamic node, a precharge device for charging the dynamic nod...
This dissertation discusses the overhead of traditional domino logic that consumes a higher cycle ti...