Add to ORKGAbstract — We present a technique, termed clockgenerating (CG) domino, for improving dual-output domino logic that reduces area, clock load, and power without increasing the delay. A delayed clock, generated from certain dual-output gates, is used to convert other dual-output gates to single output. Simulation results with ISCAS 85 benchmark circuits indicate an average reduction in area, clock load, and power of 17%, 20%, and 24 % respectively over dual-output domino and a 48 % power reduction for the largest circuit. Keywords — Domino Logic, Delayed Clocks, Low-power I
A novel technique for dual- threshold is proposed and examined with inputs and clock signals combina...
A novel technique for dual- threshold is proposed and examined with inputs and clock signals combina...
Abstract – Four different dynamic circuit techniques are proposed in this paper for lowering the act...
136 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1999.We have so far focussed on po...
136 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1999.We have so far focussed on po...
In this paper, a new technique of power reduction in CMOS domino logic is proposed. The proposed tec...
Abstract: Reduction of propagation delay is very important for high speed applications. This paper g...
Domino logic has proved to be a powerful alternative to conventional CMOS in high-performance IC des...
Abstract — In this paper, a new domino circuit is proposed, which has a lower leakage and higher noi...
125 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2002.Domino logic is known to cons...
125 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2002.Domino logic is known to cons...
In this paper, we propose a low-power true single-phase-clock (TSPC) based domino logic circuit desi...
AbstractIn this paper, we propose a low-power true single-phase-clock (TSPC) based domino logic circ...
A high performance and low power clock delayed sleep mode (CDSM) domino logic is proposed for wide f...
Leakage power and propagation delay are the two major challenges in designing CMOS VLSI circuits, in...
A novel technique for dual- threshold is proposed and examined with inputs and clock signals combina...
A novel technique for dual- threshold is proposed and examined with inputs and clock signals combina...
Abstract – Four different dynamic circuit techniques are proposed in this paper for lowering the act...
136 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1999.We have so far focussed on po...
136 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1999.We have so far focussed on po...
In this paper, a new technique of power reduction in CMOS domino logic is proposed. The proposed tec...
Abstract: Reduction of propagation delay is very important for high speed applications. This paper g...
Domino logic has proved to be a powerful alternative to conventional CMOS in high-performance IC des...
Abstract — In this paper, a new domino circuit is proposed, which has a lower leakage and higher noi...
125 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2002.Domino logic is known to cons...
125 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2002.Domino logic is known to cons...
In this paper, we propose a low-power true single-phase-clock (TSPC) based domino logic circuit desi...
AbstractIn this paper, we propose a low-power true single-phase-clock (TSPC) based domino logic circ...
A high performance and low power clock delayed sleep mode (CDSM) domino logic is proposed for wide f...
Leakage power and propagation delay are the two major challenges in designing CMOS VLSI circuits, in...
A novel technique for dual- threshold is proposed and examined with inputs and clock signals combina...
A novel technique for dual- threshold is proposed and examined with inputs and clock signals combina...
Abstract – Four different dynamic circuit techniques are proposed in this paper for lowering the act...