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In this work, parallel feedback amplifiers (PFAs) are presented as a means of generating ultra broadband logarithmic amplifiers. The low frequency gain equations and an AC model of PFAs are given. A circuit is presented for automatic, on-chip DC o#set error reduction. In addition, circuits for achieving temperature and process stable, high power, low noise logarithmic amplifiers are described. The performance simulations of a DC - 7.5 GHz logarithmic amplifier are described. The circuit has been submitted for fabrication in a 47 GHz f t silicon germanium BiCMOS process. The integrated circuit occupies 2 mm , consumes 667 mW of power from a-3.3 V supply, has 42 dB of logarithmic dynamic range, 50 ps rise/fall times, and a 12 mV/dB single ended logarithmic slope