FULL FLASH LOGARITHMIC ADC ARCHITECTURE

Abstract: The advantages of a signal processing in the logarithmic domain are recently pointed out by some authors [1,2]. On the other hand, suitable logarithmic input amplifiers are available in the literature. The traditional logarithmic amplifier configuration based on a voltage operational amplifier with a diode connected transistor in its feedback loop, which displays a significantly reduced bandwidth at lower signal levels, was modified replacing the operational amplifier by a transconductance feedback amplifier. This solution overcomes the said problem completely and offers constant-bandwidth operation throughout the full signal range [3]. Some authors have proposed algorithmic architectures for the hardware realization of logarithmic Analogue to Digital Converters (ADC) [4,5]. This paper presents a fully analogue architecture of logarithmic ADC. The proposed architecture represents a logarithmic version of the calliper rule based linear ADC recently proposed [6,7]. The main feature of this architecture is the small number of reference resistors needed, namely 3*2n/2 instead of 2n, being n the number of bits of the binary converted sample