A Floating-point Validation Suite for High-performance Shared and Distributed Memory Computing Systems

Methodology to systematically identify and isolate bugs in floating point implementation in highperformance multiple CPU computing systems is formulated. A validation suite is written and tested. Results show improper implementation. Proper implementation guidelines are suggested and prototyped. Keywords: IEEE754, Validation, Suite, NaN 1 Introduction High-performance computers often sacrifice correctness in order to achieve throughput, particularly when it comes to floating point operations. "It is the TFLOPS that count, even if a few of the trillion operations are meaningless thereby rendering the end result absurd" - seems to be the attitude of most vendors of computing equipment that deal with floating point operations. This has been observed by the author [1], as well as others [2]. The principles behind correct floating point arithmetic is universally understood and accepted [3]. Floating point Units, that are implemented in hardware at the chip level in most modern microproces..