We present a methodology for generating floating-point arithmetic hardware designs which are, for suitable applications, much reduced in size, while still retaining performance and IEEE-754 compliance. Our system uses three key parts: a profiling tool, a set of customisable floating-point units and a selection of system integration methods. We use a profiling tool for floating-point behaviour to identify arithmetic operations where fundamental elements of IEEE-754 floating-point may be compromised, without generating erroneous results in the common case. In the uncommon case, we use simple detection logic to determine when operands lie outside the range of capabilities of the optimised hardware. Out-of-range operations are handled by a sepa...
Abstract—In this paper we describe an open source floating-point adder and multiplier implemented us...
Hybrid floating-point (FP) implementations improve software FP performance without incurring the are...
Compulsory normalization of the represented numbers is a key requirement of the floating-point stand...
We present a methodology for generating floating-point arithmetic hardware designs which are, for...
The widely implemented and used IEEE-754 Floating-point specification defines a method by which floa...
ABSTRACT- In today’s scientific changes incident and rapid growth in financial, commercial, Internet...
This thesis discusses modifications to IEEE 754 floating-point units to help researchers and scienti...
The floating point standard IEEE 754 is widely implemented, but many of its capabilities are not wel...
Floating-point numbers are broadly received in numerous applications due their element representatio...
This paper presents the design and the implementation of a fully combinatorial floating point unit (...
Abstract—With the density of FPGAs steadily increasing, FPGAs have reached the point where they are ...
Many scenarios demand a high processing power often combined with a limited energy budget. A way to ...
<p>In this thesis, we design frameworks for efficient and accurate floating point computation. The p...
The floating point standard IEEE 754 is widely implemented, but many of its capabilities are not wel...
The current IEEE-754 floating point standard was adopted 23 years ago. IEEE chartered a committee to...
Abstract—In this paper we describe an open source floating-point adder and multiplier implemented us...
Hybrid floating-point (FP) implementations improve software FP performance without incurring the are...
Compulsory normalization of the represented numbers is a key requirement of the floating-point stand...
We present a methodology for generating floating-point arithmetic hardware designs which are, for...
The widely implemented and used IEEE-754 Floating-point specification defines a method by which floa...
ABSTRACT- In today’s scientific changes incident and rapid growth in financial, commercial, Internet...
This thesis discusses modifications to IEEE 754 floating-point units to help researchers and scienti...
The floating point standard IEEE 754 is widely implemented, but many of its capabilities are not wel...
Floating-point numbers are broadly received in numerous applications due their element representatio...
This paper presents the design and the implementation of a fully combinatorial floating point unit (...
Abstract—With the density of FPGAs steadily increasing, FPGAs have reached the point where they are ...
Many scenarios demand a high processing power often combined with a limited energy budget. A way to ...
<p>In this thesis, we design frameworks for efficient and accurate floating point computation. The p...
The floating point standard IEEE 754 is widely implemented, but many of its capabilities are not wel...
The current IEEE-754 floating point standard was adopted 23 years ago. IEEE chartered a committee to...
Abstract—In this paper we describe an open source floating-point adder and multiplier implemented us...
Hybrid floating-point (FP) implementations improve software FP performance without incurring the are...
Compulsory normalization of the represented numbers is a key requirement of the floating-point stand...