Double Precision Optimized Arithmetic Hardware Design for Binary & Floating Point Operands

ABSTRACT- In today’s scientific changes incident and rapid growth in financial, commercial, Internet-based applications, there is a huge demand for finding out the devices with low latency, power and area along with there is an growing need to allow computers to operate on both binary and decimal floating-point numbers. Accordingly, stipulation for decimal floating-point support is being added to the IEEE-754 Standard for Floating-Point Arithmetic. In this research work, we present the design and implementation of a decimal floating-point adder that is acquiescent with the current draft revision of this standard. The adder supports operations on 64-bit (16-digit) decimal floating-point operands [1].We provide synthesis results indicating the estimated area and delay for our design when it is pipelined to various depths